The present invention relates to a process for manufacturing a semiconductor wafer, a semiconductor wafer, a process for manufacturing a semiconductor integrated circuit device, and a semiconductor integrated circuit device and, more particularly, to a technique which is effective if applied to the so-called "epitaxial wafer manufacturing process" for forming an epitaxial layer over the surface of a semiconductor substrate body, an epitaxial wafer, a process for manufacturing a semiconductor integrated circuit device by using the epitaxial wafer, and a semiconductor integrated circuit device.
An epitaxial wafer is a semiconductor wafer which is formed with an epitaxial layer over the principal surface of a mirror-finished (or -polished) semiconductor mirror wafer (or polished wafer) by epitaxial growth. Incidentally, the epitaxial growth method is described, for example, on pp. 51 to 74 of "VLSI TECHNOLOGY", edited by S. M. Sze and issued in 1983 by McGraw-Hill. On the other hand, the polishing is described on pp. 39 to 42 of the same Publication, for example.
The epitaxial wafer is advantageous in that it is excellent in suppressing the soft errors and resisting to the latchup, and in that the gate insulating film to be formed over the epitaxial layer can have excellent breakdown characteristics to drastically reduce the defect density of the gate insulating film. Thus, application of the epitaxial wafer to the technique for manufacturing the semiconductor integrated circuit device.
As to this epitaxial wafer, there are the following two techniques.
The first technique is described on pp. 761 to 763 of "Applied Physics, Vol. 60, No. 8", issued on Aug. 10, 1991 by Japanese Association of Applied Physics. There is described an epitaxial wafer, in which a p.sup.+ -type (or n.sup.+ -type) semiconductor substrate is formed thereover with a p- (or n-) type epitaxial layer containing a p- (or n-) type impurity having a lower concentration than the p- (or n-) type impurity concentration of the semiconductor substrate.
In this case, there is described the structure in which a semiconductor region called the "well" is formed in the epitaxial layer and is formed thereover with a MOS FET. Since the well of this case is formed by the diffusion of the impurity from the surface of the epitaxial layer, the impurity concentration in the well is distributed to be high in the surface and low in its inside.
The second technique is described in Japanese Patent Laid-Open No. 260832/1989, for example and is directed to an epitaxial wafer which has a p-type epitaxial layer over a p-type semiconductor substrate. In this case, an element forming diffusion layer is formed to extend from the surface of the epitaxial layer to the upper portion of the semiconductor substrate.
Also described is a process, in which the semiconductor substrate body is doped at the time of forming the diffusion layer with a diffusion layer forming impurity so that simultaneously with the growth of the epitaxial layer over the semiconductor substrate body, the impurity in the upper portion of the semiconductor substrate body may be diffused to form the diffusion layer.
The distribution of the impurity concentration of this case is made to have such a plateau curve having a peak at the boundary between the epitaxial layer and the semiconductor substrate body that the impurity concentration is low at the surface side of the epitaxial layer, high at the boundary between the epitaxial layer and the semiconductor substrate body and low in the semiconductor substrate body.
The semiconductor integrated circuit device manufactured according to the aforementioned first technique is excellent in performance and reliability but has a problem in the cost because the semiconductor substrate used contains an (p.sup.+ -type or n.sup.+ -type) impurity in high concentration, is expensive, because an epitaxial layer having a large thickness is formed over the semiconductor substrate.
According to the aforementioned second technique, on the other hand, the diffusion layer is formed by the so-called "upper diffusion" to diffuse the impurity in the upper portion of the semiconductor substrate. As a result, the impurity concentration is so difficult to set that there arise a problem that the diffusion layer forming accuracy drops. Another problem is that it is obliged to change the LSI (i.e., Large Scale Integration circuit) manufacturing process using the so-called "mirror wafer".